Cache Management

1 Cache controller port
2 Configuration
3 Initialization
4 Cache Operations

µC/CPU contains a minimal cache management API to support applications and drivers performing DMA operations on cache enabled processors.

Cache controller port

Available implementations are location in the Cache directory of the µC/CPU distribution. Ports are usually divided in two parts, a toolchain independent C file and toolchain specific file. For example the ARM Cortex-A generic L1 cache controller has the following directory structure :

\uC-CPU
	\Cache
		\ARM
			\armv7_generic_l1
				\GNU
					\cpu_cache_armv7_generic_l1.S
				\IAR
					\cpu_cache_armv7_generic_l1_s.s
				\RealView
					\cpu_cache_armv7_generic_l1.s
				\cpu_cache_armv7_generic_l1.c

Configuration

After including the necessary files cache management can be enabled by setting CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED in cpu_cfg.h.

Initialization

The µC/CPU cache management module only performs cache maintenance operations. All the necessary steps to enable a processor's cache controllers must have been performed before calling CPU_Init().

Cache Operations

The cache API supports two operations to flush or invalidate a range of addresses from the data cache. See the reference manual sections for CPU_DCACHE_RANGE_FLUSH and CPU_DCACHE_RANGE_INV for details.