uC-CPU Release Notes

Owned by Former user (Deleted)
Last updated: Jul 19, 2021 by WES Admin
5 min read

Version 1.32.01

Release Date

May 4, 2021

New Features and Improvements

  • POSIX port - Capitalized folder and added _POSIX_C_SOURCE.

Version 1.32.00

Release Date

February 28, 2020

  • Open-source Release

Version 1.31.05

Release Date

June 20, 2019

New Features and Improvements

  • [621] ARMv7-R port - Added GNU toolchain support.
  • [622] ARMv7-R port - Simplified the port by removing unused routines which should now be handled by third-party libraries.

Bugfixes

  • [612] ARMv7-M port - Fixed build error in the CCS toolchain definitions for the memory barrier macros.

Version 1.31.04

Release Date

December 7, 2018

Improvements

  • [423] ARMv6-M port - CPU_IntSrcPrioSet() now calculates the priority offsets internally. 
  • [530] ARMv7-M port - CPU_IntSrcPrioSet() now calculates the priority offsets internally. 

Version 1.31.03

Release Date

June 18, 2018

New Features

  • [422] ARMv7-M Non-Kernel-Aware Interrupt Support

Improvements

  • [109][154] ARM port directories have been restructured and consolidated (e.g. ARM-Cortex-A/ARMv7-A, ARM-Cortex-A/ARMv8-A)

Bug Fixes

  • [218] ARMv7 cache routine missing Break
  • [263] Cache functions for ARM and Kinetis should return immediately when the length is 0
  • [313] Microblaze cache functions are declared implicitly

Deprecations

  • [411] Deprecated the ARM-Cortex-M1 port

Version 1.31.02

Release Date

December 8, 2017

New Features

  • [199] Added a new port for the RISC-V architecture

Bug Fixes

  • [158] Fixed a compiler warning in CCS where __DSB() could not be found.

Version 1.31.01

Release date : 2016-11-30

Requirements

  • µC/LIB V1.38.02

New features & improvements

  • Core
    • MISRA C:2012
      • Updated the core for improved MISRA C:2012 compliance.
      • The number of violations has been reduced to 8 required rules and 8 advisory rules.
  • ARC EM6
    • New port for the Synopsys ARC EM6. Supports the MetaWare toolchain.

Bug Fixes

  • ARM-Cortex-M3
    • Fixed improper calculation of the vector position in the CPU_Int*** functions.
    • Increased the data type size for the maximum position to 16-bits in order to support a full vector table.

  • ARM-Cortex-M4
    • Increased the data type size for the maximum position to 16-bits in order to support a full vector table. 

Version 1.31.00

Release date : 2016-06-30

Requirements

  • µC/LIB V1.38.02

New features & improvements

  • ARM-Cortex-A
    • Critical sections for GCC now use inline assembly.
  • ARM-Cortex-A50
    • Added CP15 accessors.
  • C28x
    • New port for the CCS toolchain.
  • eSi-3250
    • New port for the EDS toolchain.
  • MicroBlaze
    • Changed the extension of cpu_a.s to cpu_a.S.
    • Added support for Microblaze cores without the MSR instruction.
    • Implemented an optimized CLZ for the port.
  • MPC57xx
    • New port for the GNU toolchain.
  • MSP430x
    •  Added support for CCS.
  • Cache
    • Added cache support for the Cortex-M7.
    • Added cache support for the PowerPC e200z4204n3 core on the GNU toolchain.
  • Core
    • Added a function to reset performance monitors, CPU_StatReset().
    • Added a C linkage specifier to cpu_core.h for C++ builds.
    • CPU_VAL_UNUSED(val) now uses (void)(val) for suppressing unused variable warnings.
    • CPU_CACHE_MGMT_EN is now given a default value if not defined.

Bug fixes

  • ARM-Cortex-A
    • Fixed endianness detection in the CCS port.
  • ARM-Cortex-M3
    • Fixed vector position calculations.
  • POSIX
    • Fixed race condition when manually triggering an interrupt.
  • Cfg Template
    • Fixed typedefs for 64 bit Address and Data sizes.

Obsolete features

  • The following CPU ports have been removed and replaced by the ARM-Cortex-A port.
    • ARM-Cortex-A8
    • ARM-Cortex-A9

Version 1.30.02

Release date : 2015-02-16

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • ARM-Cortex-A50: RealView port updated for ARM Compiler 6
  • ARM-Cortex-A50: GNU-like toolchain support
  • ARM-Cortex-A: Endianness now detected at compile time
  • ARM-Cortex-M4: Port for Texas Instrument Code Composer Studio
  • MicroBlaze: Support for both little and big endian version of the MicroBlaze
  • MicroBlaze: Memory barrier implementation
  • RL78: Port for the GNU toolchain
  • Freescale Kinetis: Cache controller implementation for the Kinetis
  • NiosII: Cache controller implementation for the Altera Nios II
  • POSIX: Port for POSIX like systems
  • Core: New function CPU_PopCnt32()

Bug fixes

  • (CPU-81) Cache: Conditional inclusion of cpu_cache.h now checks if CPU_CFG_CACHE_MGMT_EN is defined to prevent compiler warnings
  • (CPU-93) ARM-Cortex-M0 & M1: Added missing include of intrinsics.h in the IAR port
  • (CPU-96) ARM-Cortex-A50: Fixed incorrect nesting of critical sections
  • (CPU-97) ARM-Cortex-A: Fixed interworking linking issues under the GNU toolchain
  • (CPU-104) RL78: CPU_SR() in the GNURX port now defined as a byte to save stack space
  • (CPU-106) ARM-Cortex-M3 & M4: Added missing critical section exit in function CPU_IntSrcPrioGet()
  • (CPU-107) Fixed shift by zero warning for the macro CPU_TYPE_CREATE
  • (CPU-109) Fixed endian detection at compile type
  • (CPU-113) Cache: Modified the name of the ARM cache controller ports to ensure unique filenames
  • (CPU-118) CPU_CntLeadZeroes32: Fixed incorrect cast for less than 32 bit platforms
  • (CPU-119) Win32: Removed the space in the Visual Studio port path

Version 1.30.01.01

Release date : 2014-02-18

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • MIPS32-4k: Various improvements and bug fixes.
    • Implementation of assembly optimised version of CPU_CntLeadZeros(). Improves performance when used in conjunction with uC/OS-III
    • Implementation of the memory barrier macros
    • Removed outdated code directives and various other aesthetic improvements
    • Bug fixes (See below)

Bug fixes

  • (CPU-90) MIPS32-4k: Added required hazard barriers at the end of the critical sections
  • (CPU-88) MIPS32-4k: Added missing .noreorder code generation directive in cpu_a.s
  • (CPU-82) Improved MISRA compliance of CPU_CntLeadZerosXX() functions

Version 1.30.01

Release date : 2014-02-12

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • ARM-Cortex-A50: New port for the Cortex-A50 line of 64 bits ARMv8-A processors. Includes support for the ARM Compiler Toolchain and GNU

Bug fixes

  • (CPU-69) Cache: Fixed incorrect declaration of CPU_DCache_LineSizeGet()
  • (CPU-78) Cache: Fixed incorrect reference to CPU_CacheMGMT_LineSize in the IAR implementation of cpu_cache_armv7_generic_l1
  • (CPU-79) Missing CRITICAL_SECTION_EXIT() in CPU_IntSrcPrioGet()
  • (CPU-80) MISRA compliance fix in the definition of CPU_WORD_SIZE_XX
  • (CPU-84) Added missing empty memory barriers in the port template

Version 1.30.00

Release date : 2013-12-18

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • Cache maintenance: Cache maintenance functionalities are now implemented in uC/CPU for use by other Micrium products.
  • Cortex-M3 & M4: Performance improvements for the IAR toolchain.
  • Online documentation: The reference manual is now available online. Please visit micrium.atlassian.net for the latest version.

Bug fixes

  • (CPU-59) Renesas RX: Added missing definition of CPU_CFG_STK_ALIGN_BYTES.
  • (CPU-64, CPU-68) Renesas RX: Added missing definitions of the memory barrier macros.

Version 1.29.02.04

Release date : 2013-09-24

Requirements

  • µC/LIB V1.35.00

Bug fixes

  • (CPU-46) Cortex-A: Incorrect preprocessor condition to detect the endianness of the GNU and CCS ports.
  • (CPU-47) Cortex-A9: Incorrect preprocessor condition to detect the endianness of the GNU and CCS ports.

Version 1.29.02.03

Release date : 2013-08-06

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • ARM Cortex-A: New port for the entire 32-bits ARM Cortex-A family. Support for the following compilers/toolchains is included:
    • ARM Compilation Tools (DS-5)
    • GNU
    • IAR EWARM
    • TMS470 Compiler Toolchain (TI Code Composer Studio)
  • C++ compilation: Building in C++ now supported for all the ports.

Bug fixes

  • (CPU-40) Renesas RX: CPU_CFG_KA_IPL_BOUNDARY should be defined to a default value when left unconfigured.
  • (CPU-39) Incorrect file extension for some GCC assembler files. The following ports were affected:
    • AVR32/UC3
    • AVR32/AP7000
    • ARM-Cortex-M4
    • MCF5272
  • (CPU-35) Cortex A9: Invalid files in the IAR port.

Deprecated features

  • The following CPU ports are now supported by the new ARM-Cortex-A port and will be removed in a future release.
    • ARM-Cortex-A8
    • ARM-Cortex-A9

Version 1.29.02.02

Release date : 2013-05-22

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • POSIX: New port for testing on POSIX and POSIX-like systems.

Bug fixes

  • (CPU-30) Renesas RX: IAR port should use __set_interrupt_level() instead of __set_interrupt_state().
  • (CPU-32) Renesas RX: Invalid quote characters in GNURX/cpu.h.

Version 1.29.02.01

Release date : 2013-04-18

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • Renesas RX: Support for improved uCOS-III port and interrupt handling.

Bug fixes

  • (CPU-24) Cortex-R4: Missing include of intrinsics.h in the IAR port.

Version 1.29.02

Release date : 2013-03-18

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • ARMv7 memory barriers: New memory barriers implementation for the Cortex A, R and M ports.
  • Stack alignment: New cpu specific define CPU_STK_ALIGN_BYTES for the platform required stack alignment.
  • Cortex A8: New port for the IAR toolchain.
  • Cortex A9: New port for the RealView/ARMCC toolchain.
  • Endianness test: New global constant CPU_EndiannessTest for testing endianness at runtime.

Bug fixes

  • (CPU-20) Renesas RX: Volatile registers require the __evenaccess type qualifier on RXC.
  • (CPU-15) cpu_bsp.c not buildable by default.
  • (CPU-13) ARMv7-AR: Add missing data synchronisation barriers in critical sections.
  • (CPU-6) Cortex-M: Interrupt priority incorrectly set for the M0, M3 and M4 ports.

Version 1.29.01.01

Release date : 2012-12-03

Requirements

  • µC/LIB V1.35.00

New features & improvements

  • Renesas RX port: New unified port for most of the Renesas RX series other than the RX610.
  • Configurable endianness: CPU endianness can now be configured in cpu_cfg.h for bi-endian architectures. Currently only the RX port supports this feature.

API Changes

  • N/A

Bug fixes

  • N/A

Deprecated features

  • The following CPU architectures are now supported by the new RX port and will be removed in a future release. Note that the RX610 still requires a separate port.
    • RX210
    • RX62N
    • RX63N
    • RX600
    • RX630

Deprecated features

  • The following CPU ports are now supported by the new ARM-Cortex-A port and will be removed in a future release.
    • ARM-Cortex-A8
    • ARM-Cortex-A9