uC-CPU Release Notes

New features & improvements

• Core
  • MISRA C:2012
    • Updated the core for improved MISRA C:2012 compliance.
    • The number of violations has been reduced to 8 required rules and 8 advisory rules.
• ARC EM6
  • New port for the Synopsys ARC EM6. Supports the MetaWare toolchain.

Bug Fixes

• ARM-Cortex-M3
  • Fixed improper calculation of the vector position in the CPU_Int*** functions.
  • Increased the data type size for the maximum position to 16-bits in order to support a full vector table.
  
  
• ARM-Cortex-M4
  • Increased the data type size for the maximum position to 16-bits in order to support a full vector table. 

New features & improvements

• ARM-Cortex-A
  • Critical sections for GCC now use inline assembly.
• ARM-Cortex-A50
  • Added CP15 accessors.
• C28x
  
  • New port for the CCS toolchain.
• eSi-3250
  • New port for the EDS toolchain.
• MicroBlaze

• • Changed the extension of cpu_a.s to cpu_a.S.
  • Added support for Microblaze cores without the MSR instruction.
  • Implemented an optimized CLZ for the port.
• MPC57xx
  • New port for the GNU toolchain.
• MSP430x
  •  Added support for CCS.
• Cache
  • Added cache support for the Cortex-M7.
  • Added cache support for the PowerPC e200z4204n3 core on the GNU toolchain.
• Core
  • Added a function to reset performance monitors, CPU_StatReset().
  • Added a C linkage specifier to cpu_core.h for C++ builds.
  • CPU_VAL_UNUSED(val) now uses (void)(val) for suppressing unused variable warnings.
  • CPU_CACHE_MGMT_EN is now given a default value if not defined.

Bug fixes

• ARM-Cortex-A
  • Fixed endianness detection in the CCS port.
• ARM-Cortex-M3
  • Fixed vector position calculations.
• POSIX
  • Fixed race condition when manually triggering an interrupt.
• Cfg Template
  • Fixed typedefs for 64 bit Address and Data sizes.
    

Obsolete features

• The following CPU ports have been removed and replaced by the ARM-Cortex-A port.
• ARM-Cortex-A8
• ARM-Cortex-A9
  

New features & improvements

• ARM-Cortex-A50: RealView port updated for ARM Compiler 6
• ARM-Cortex-A50: GNU-like toolchain support
• ARM-Cortex-A: Endianness now detected at compile time
• ARM-Cortex-M4: Port for Texas Instrument Code Composer Studio
• MicroBlaze: Support for both little and big endian version of the MicroBlaze
• MicroBlaze: Memory barrier implementation
• RL78: Port for the GNU toolchain
• Freescale Kinetis: Cache controller implementation for the Kinetis
• NiosII: Cache controller implementation for the Altera Nios II
• POSIX: Port for POSIX like systems
• Core: New function CPU_PopCnt32()

Bug fixes

• (CPU-81) Cache: Conditional inclusion of cpu_cache.h now checks if CPU_CFG_CACHE_MGMT_EN is defined to prevent compiler warnings
• (CPU-93) ARM-Cortex-M0 & M1: Added missing include of intrinsics.h in the IAR port
• (CPU-96) ARM-Cortex-A50: Fixed incorrect nesting of critical sections
• (CPU-97) ARM-Cortex-A: Fixed interworking linking issues under the GNU toolchain
• (CPU-104) RL78: CPU_SR() in the GNURX port now defined as a byte to save stack space
• (CPU-106) ARM-Cortex-M3 & M4: Added missing critical section exit in function CPU_IntSrcPrioGet()
• (CPU-107) Fixed shift by zero warning for the macro CPU_TYPE_CREATE
• (CPU-109) Fixed endian detection at compile type
• (CPU-113) Cache: Modified the name of the ARM cache controller ports to ensure unique filenames
• (CPU-118) CPU_CntLeadZeroes32: Fixed incorrect cast for less than 32 bit platforms
• (CPU-119) Win32: Removed the space in the Visual Studio port path

New features & improvements

• MIPS32-4k: Various improvements and bug fixes.
  
  • Implementation of assembly optimised version of CPU_CntLeadZeros(). Improves performance when used in conjunction with uC/OS-III
  • Implementation of the memory barrier macros
  • Removed outdated code directives and various other aesthetic improvements
  • Bug fixes (See below)

Bug fixes

• (CPU-90) MIPS32-4k: Added required hazard barriers at the end of the critical sections
• (CPU-88) MIPS32-4k: Added missing .noreorder code generation directive in cpu_a.s
• (CPU-82) Improved MISRA compliance of CPU_CntLeadZerosXX() functions

New features & improvements

• ARM-Cortex-A50: New port for the Cortex-A50 line of 64 bits ARMv8-A processors. Includes support for the ARM Compiler Toolchain and GNU

Bug fixes

• (CPU-69) Cache: Fixed incorrect declaration of CPU_DCache_LineSizeGet()
• (CPU-78) Cache: Fixed incorrect reference to CPU_CacheMGMT_LineSize in the IAR implementation of cpu_cache_armv7_generic_l1
• (CPU-79) Missing CRITICAL_SECTION_EXIT() in CPU_IntSrcPrioGet()
• (CPU-80) MISRA compliance fix in the definition of CPU_WORD_SIZE_XX
• (CPU-84) Added missing empty memory barriers in the port template