µC/TCP-IP Memory Management

One of the most important aspects of writing a device driver is the memory management since each type of device driver should at least validate the interface memory configuration as shown in Memory Configuration. The device driver developer could use the memory configuration of the interface during the initialization to allocate memory usage uniquely within the device driver.

See µC/TCP-IP Network Interface Configuration for further information about the memory management and it’s configuration.

For non-DMA based devices, additional memory allocation from within the device driver may not be necessary. However, DMA based devices should allocate memory from the µC/LIB memory module for descriptors. By using the µC/LIB memory module instead of declaring arrays, the driver developer can easily align descriptors to any required boundary and benefit from the run-time flexibility of the device configuration structure.

If you have access to the source code, see the µC/LIB documentation for additional information and usage notes.

Net_dev_cfg_<controller>.c/.h is used to specify how much memory should be reserved by the µC/TCP-IP module for the device buffer and where to map it. As Network Packet Transmission Overview shows, the memory regions are managed by the core (NetBuf layer) which uses the µC/LIB memory module. The IF layer creates the memory pools for all configured buffers as per the information in Net_dev_cfg_<controller>.c.

When the driver requires additional memory, it is the responsibility of the developer to create the additional memory pools. For example, when your device supports DMA access, you have to reserve memory for the Receive/Transmit descriptors. As all memory pools are managed using µC/LIB, when you increase some device configuration value, the heap size of µC/LIB must follow the value modification. If not done properly, the µC/TCP-IP module will run out of memory during the initialization or too much memory will be reserved by µC/LIB.

µC/TCP-IP has been designed to operate with several device driver memory configurations. There are four possible memory configuration arrangements which are shown below:

CPU with an Internal Media Access Controller (MAC)

When a packet is received by the MAC, a DMA transfer from the MAC’s internal buffer into main memory is initiated by the MAC. This method generally provides for shortened development time and excellent performance.

CPU with an Internal MAC but with Dedicated Memory

When a packet is received, the MAC initiates a DMA transfer into dedicated memory. Generally, most configurations of this type allow for transmission from main memory while reserving dedicated memory for either receive or transmit operations. Both the MAC and the CPU can read and write from dedicated memory and so the stack can process packets directly from dedicated memory. Porting to this architecture is generally not difficult and provides for excellent performance. However, performance may be limited by the size of the dedicated memory; especially in cases where transmit and receive operations share the dedicated memory space.

Cooperative DMA solution where both the CPU and MAC take part in the DMA operation

This configuration is generally found on external devices that are either connected directly to the processor bus or connected via the ISA or PCI standard. This method requires that the CPU contain a DMA peripheral that can be configured to work within the architectural limitations of the external device. This method is more difficult to port to, but generally offers excellent performance.

External device attached via the CPU’s External bus

Data is moved between main memory and the external device’s internal memory via bus read and write cycles. The amount of data transferred in a given bus operation depends on the width of the data bus. This method requires additional CPU intervention in order to copy all of the data to and from the device when necessary. This method is generally easy to port and offers average performance.

These settings are likely to be influenced by the size of the available memory on the device. You will have to find these specific configuration values for the device driver and provide them to the stack user. An example of a typical device and buffer configuration is available in Performance Issues. The size and number of receive and transmit buffers depends on many factors, including, but not limited to:

• The desired level of performance
• The bandwidth required for the application
• CPU utilization