Ethernet - Transmitting and Receiving using DMA

A DMA controller is a device that moves data through a system independently of the CPU/MCU. It connects internal and peripheral memories via a set of dedicated buses. A DMA controller can also be considered a peripheral itself in the sense that the processor programs it to perform data transfers.

In general, a DMA controller includes an address bus, a data bus, and control registers. An efficient DMA controller possesses the ability to request access to any resource it needs, without involving the CPU. It must have the capability to generate interrupts and to calculate addresses.

A processor might contain multiple DMA controllers, multiple DMA channels, and multiple buses that link the memory banks and peripherals directly. Processors with an integrated Ethernet controller typically have a DMA controller for their Ethernet hardware.

Generally, the processor should need to respond to DMA interrupts only after the data transfers are completed. The DMA controller is programmed by the processor to move data in parallel while the processor is doing its regular processing tasks.

Since the DMA controller has the capability to interface with memory, it can get its own instruction from memory. Picture a DMA controller as a simple processor with a simple instruction set. DMA channels have a finite number of registers that need to be filled with values, each of which gives a description of how to transfer the data.

There are two main classes of DMA transfer: Register Mode and Descriptor Mode. In Register mode, the DMA controller is programmed by the CPU by writing the required parameters in the DMA registers. In Descriptor mode, the DMA can use its read memory circuitry to fetch the register values itself rather than burdening the CPU to write the values. The blocks of memory containing the required register parameters are called descriptors. When the DMA runs in Register Mode, the DMA controller simply uses the values contained in the registers.

Descriptor Mode provides the best results, and is mostly found in microprocessor/ microcontroller DMA controllers with integrated Ethernet controller. This is the mode described in detail below.

Descriptor Mode

In Descriptor Mode, the formatting of the descriptor information is provided by the DMA controller. The descriptor contains all of the same parameters that the CPU (operating in Register Mode) would program into the DMA control registers.

Descriptor Mode allows multiple DMA sequences to be chained together so the controller can be programmed to automatically set up and start another DMA transfer after the current sequence completes. The descriptor-based model provides the most flexible configuration to manage a system’s memory.

The DMA controller provides a main descriptor model method; normally called a Descriptor List. Depending on the DMA controller, the descriptor list may reside in consecutive memory locations, but this is not mandatory. µC/TCP-IP reserves consecutive memory blocks for descriptors and both models can be used.

The vast majority of processors that include Ethernet support come with a Direct Memory Access Controller (DMAC). This has the advantage reducing the load on the CPU, as the DMAC handles data transfers from the CPU internal memory to the Ethernet controller memory area or vice versa. If a DMAC is present on your device, we encourage you to take advantage of it.In the µC/TCP-IP device driver, a linked list of descriptors is created, as shown in the figure above. The term linked implies that one descriptor points to the next descriptor, which is loaded automatically. To complete the chain, the last descriptor points back to the first descriptor, and the process repeats. This mechanism is used for Ethernet frame reception.