Concepts

Several aspects of the µC/TCP-IP driver architecture that are discussed in this chapter include:

Network Interface

The network interface is the physical and logical implementation. Currently, only network interfaces which use the IEEE 802.3 and/or Ethernet standards are supported.

Device Driver

A device driver is an interface between the common API of the µC/TCP-IP stack and the device specific architecture and available resources (RAM, DMA, IO, Peripheral Registers, etc…).

Ethernet Device Layer

The device layer of the Ethernet device driver implements functions to control the Media Access Controller (MAC). µC/TCP-IP supports internally wired Ethernet controllers and externally wired Ethernet controllers connected to an Ethernet PHY. This layer implements functionality required by other network interface layers which are specific to the device and not to the board such as initializing, receiving and transmitting. This layer may implement functionally by setting and using controller register, DMA, or memory copy.

Ethernet PHY Layer

PHY is the physical layer of the TCP/IP stack model between the Media Access Controller (MAC) and physical medium of the network (copper, optical fiber or RF). The PHY accomplishes two tasks: the first is to encode the transmitted data and decode received data; the second is to drive and read the medium with respect to bit timing, signal level and modulation.

Wireless Device Layer

The device layer of the wireless device driver implements functions to control the Media Access Controller (MAC) as a wireless module. µC/TCP-IP only supports wireless modules that include an integrated wireless supplicant (which is responsible for making login requests) and communicates via SPI. Additionally, the packet format used by the module must be 802.3 or Ethernet. This layer implements functionality required by other network interface layers which are specific to the device and not to the board such as initializing, receiving and transmitting. This layer may implement functionally by writing and reading in the wireless device register through SPI.

Wireless Manager

The Wireless Manager is a set of internal mechanisms to perform management operations on the wireless module such as scan, join, leave, and so on.

Direct Memory Access (dma)

Direct Memory Access controller is a common hardware feature of processors and microcontrollers. DMA allows copying memory blocks from peripherals and internal memory while offloading the processor. An interrupt is generated when the transfer is completed to notify the CPU when a data transfer is completed.

Memory Copy

In the case where the processor doesn’t have DMA controllers, all memory transfers have to be executed by the processor. This method is called Memory Copy. It is less efficient than DMA transfers because the CPU has to move each element of the data, whereas it could do other tasks if a DMA was available to perform the data transfer.

SPI

SPI (Serial Peripheral Interface) is a synchronous serial data link used by peripherals commonly built-in to CPUs. Since the communication can easily be accomplished by software control of GPIO pins (“software SPI” also known as “bit-banging”), SPI devices can be connected to almost any platform. Any SPI device uses four signals, which are used to communicate with the host (CS, DataIn, CLK and DataOut).

The four signals connecting the host and device (also known as master and slave) are named variously in different manuals and documents. The MOSI pin (Master Out Slave In) may be called DI on device pinouts; similarly, MISO pin (Master In Slave Out) may be called DO on device pinouts. The CS and CLK pins (also known as SSEL and SCK) are the chip select and clock pins. The host selects the slave by asserting CS, potentially allowing it to choose a single peripheral among several that are sharing the bus (i.e., by sharing the CLK, MOSI and MISO signals).