ATA (True IDE) Communication

The interface between an ATA device and host is comprised of data bus, address bus and various control signals, as shown in Figure - True IDE (ATA) host/device connection. Three forms of data transfer are possible, each with several timing modes:

• 1 PIO (programmed input/output). PIO must always be possible; indeed, it may be the only possible transfer form on certain hardware. Using PIO, data requests are satisfied by direct reads or writes to the DATA register. The IDENTIFY_DEVICE command and standard sector and multiple sector read/write commands always involve this type of transfer. Five timing modes (0, 1, 2, 3 and 4) are standard; two more (5 and 6) are defined in the CF specification.
• 2 Mutiword DMA. In Multiword DMA mode, a DMARQ and –DMACK handshake initiates automatic data transmission, during which the host moves data between its memory and the bus. The DMA read/write commands (READ_DMA, WRITE_DMA) may use Multiword DMA. Three timing modes (0, 1 and 2) are standard; two more (3 and 4) are defined in the CF specification.

• 3 Ultra DMA. The purposes of several control signals are reassigned during Ultra DMA transfers. For example, IORDY becomes either DDMARDY or DSTROBE (depending on the direction) to control data flow. The DMA read/write commands (READ_DMA, WRITE_DMA) may use Ultra DMA. Seven timing modes (0, 1, 2, 3, 4, 5 and 6) are standard.

The host controls the device via eight registers (see Figure - Register definitions). Seven of these registers comprise the command block: FR, SC, SN, CYL, CYH, DH and CMD. The command block registers are written, in sequence, to execute a command. Afterwards, the error and status register return to the host a failure indicator or otherwise signal device operation completion. The need to poll these registers is removed if the host is instead alerted by an interrupt request (on the INTRQ signal) to attend to the device.

Up to two devices, known as master and slave (or device 0 and device 1) may be located on a single conventional bus. The active device (the target for the next command) is selected by the DEV bit in the DH register, and generally only one device can be accessed at a time, meaning that a read or write to one cannot interrupt a read or write to the other.