FS_DEV_NOR_CFG

typedef struct fs_dev_nor_cfg {

    CPU_ADDR            AddrBase; 

    CPU_INT08U          RegionNbr; 

    CPU_ADDR            AddrStart; 

    CPU_INT32U          DevSize; 

    FS_SEC_SIZE         SecSize; 

    CPU_INT08U          PctRsvd; 

    CPU_INT16U          EraseCntDiffTh; 

    FS_DEV_NOR_PHY_API *PhyPtr; 

    CPU_INT08U          BusWidth; 

    CPU_INT08U          BusWidthMax; 

    CPU_INT08U          PhyDevCnt; 

    CPU_INT32U          MaxClkFreq; 

  } FS_DEV_NOR_CFG;

Configures the properties of a NOR device that will be opened. A pointer to this structure is passed as the second argument of FSDev_Open() for a NOR device.

Members

AddrBase

must specify

1. the base address of the NOR flash memory, for a parallel NOR.

2. 0x00000000 for a serial NOR.

RegionNbr

must specify the block region which will be used for the file system area. Block regions are enumerated by the physical-layer driver; for more information, see the physical-layer driver header file. (on monolithic devices, devices with only one block region, this must be 0).

AddrStart

must specify

1. the absolute start address of the file system area in the NOR flash memory, for a paralel NOR.

2. the offset of the start of the file system in the NOR flash, for a serial NOR.

The address specified by AddrStart must lie within the region RegionNbr.

DevSize

must specify the number of octets that will belong to the file system area.

SecSize

must specify the sector size for the NOR flash (either 512, 1024, 2048 or 4096).

PctRsvd

must specify the percentage of sectors on the NOR flash that will be reserved for extra-file system storage (to improve efficiency). This value must be between 5% and 35%, except if 0 is specified whereupon the default will be used (10%).

EraseCntDiffTh

must specify the difference between minimum and maximum erase counts that will trigger passive wear-leveling. This value must be between 5 and 100, except if 0 is specified whereupon the default will be used (20).

PhyPtr

must point to the appropriate physical-layer driver:

FSDev_NOR_AMD_1x08

CFI-compatible parallel NOR implementing AMD command set, 8-bit data bus.

FSDev_NOR_AMD_1x16

CFI-compatible parallel NOR implementing AMD command set, 16-bit data bus.

FSDev_NOR_Intel_1x16

CFI-compatible parallel NOR implementing Intel command set, 16-bit data bus

FSDev_NOR_SST39

SST SST39 Multi-Purpose Flash

FSDev_NOR_STM25

ST M25 serial flash

FSDev_NOR_SST25

SST SST25 serial flash

Other

User-developed

For a parallel NOR, the bus configuration is specified via BusWidth, BusWidthMax and PhyDevCnt:

BusWidth

is the bus width, in bits, between the MCU/MPU and each connected device.

BusWidthMax

is the maximum width supported by each connected device.

PhyDevCnt

is the number of devices interleaved on the bus.

For a serial flash, the maximum clock frequency is specified via MaxClkFreq.

Notes

None.