Part Layer

There are two different part-layer implementations distributed with the NAND driver (Table - Part-layer implementations provided).

Driver API

Files

Description

FS_NAND_PartStatic

fs_dev_nand_part_static.* in /Micrium/Software/uC-FS/Dev/NAND/Part

Manually configure the parameters of each NAND flash device you use.

FS_NAND_PartONFI

fs_dev_nand_part_onfi.* in /Micrium/Software/uC-FS/Dev/NAND/Part

Use the parameters automatically obtained by reading the parameter page of ONFI-compliant NAND flash devices.


It is mandatory to use one part-layer implementation for the NAND driver to work. It is recommended to use one of the provided implementations.

Statically configured part layer

This part-layer implementation is the basic one. It lets you set all the physical characteristics of the device through a configuration structure of type FS_NAND_PART_STATIC_CFG. Typically, the pointer to the configuration structure is then assigned to the field .PartCfgPtr of the translation layer configuration structure (see NAND Translation Layer). The pointer to the translation layer configuration structure can then be passed as an argument to the function FSDev_Open(). Refer to Getting Started for an example of configuration. The part configuration structure should be initialized to FS_NAND_PartStatic_DfltCfg to ensure upward compatibility with future versions. The configuration fields available for the static part layer are described in Listing - NAND static part layer configuration structure:

Listing - NAND static part layer configuration structure
typedef  struct  fs_nand_part_static_cfg {
    FS_NAND_BLK_QTY            BlkCnt;                      (1)
    FS_NAND_PG_PER_BLK_QTY     PgPerBlk;                    (2)
    FS_NAND_PG_SIZE            PgSize;                      (3)
    FS_NAND_PG_SIZE            SpareSize;                   (4)
    CPU_INT08U                 NbrPgmPerPg;                 (5)
    CPU_INT08U                 BusWidth;                    (6)
    CPU_INT08U                 ECC_NbrCorrBits;             (7)
    FS_NAND_PG_SIZE            ECC_CodewordSize;            (8)
    FS_NAND_DEFECT_MARK_TYPE   DefectMarkType;              (9)
    FS_NAND_BLK_QTY            MaxBadBlkCnt;               (10)
    CPU_INT32U                 MaxBlkErase;                (11)
    FS_NAND_FREE_SPARE_DATA   *FreeSpareMap;               (12)
} FS_NAND_PART_STATIC_CFG;


(1) Number of blocks in your device.

(2) Number of pages per block in your device.

(3) Page size (in octets) of your device.

(4) Size of the spare area (in octets) of your device.

(5) Number of partial page programming allowed before an erase operation (for example, it would be set to 4 if a device with 2048 octets pages could be written in 4 accesses of 512 octets).

(6) Number of input/output lines of the device’s bus.

(7) Minimum required number of correctable bits per codeword for the ECC.

(8) Codeword size required for ECC. The codeword size corresponds to the maximum data size (in octets) that must be sent to the ECC calculation module to get a single error correction code.

(9) Factory defect mark type. This determines how the translation layer can detect if a block factory is marked as a defect block. The possible values are listed below. Unless otherwise specified, any unset bit in the defect mark indicates a defective block. A byte refers to an 8-bit value, a word refers to a 16-bit value and a location is a bus width wide value (byte for 8-bit bus and word for 16-bit bus).

DEFECT_SPARE_L_1_PG_1_OR_N_ALL_0: the defect mark is in the first location of the spare area (first byte or first word, depending on bus width) of the first or last page. If the mark reads 0, the block is defective.

DEFECT_SPARE_ANY_PG_1_OR_N_ALL_0: any location in the spare area or the first or last page equal to 0 indicates a defective block.

DEFECT_SPARE_B_6_W_1_PG_1_OR_2: the defect mark is the sixth byte or the first word of the spare area (depending on bus width) of the first or second page.

DEFECT_SPARE_L_1_PG_1_OR_2: the defect mark is the first location in the spare area of the first or second page.

DEFECT_SPARE_B_1_6_W_1_IN_PG_1: the defect mark is the first and sixth byte or the first word of the spare area (depending on bus width) of the first page.

DEFECT_PG_L_1_OR_N_PG_1_OR_2: the defect mark is the first or last location of the page area in the first or second page.

(10) Maximum number of bad blocks within a single device during its lifetime.

(11) Maximum number of erase operations that can be performed on a single block.

(12) Pointer to the map of the free regions in the spare area (see listing below).

Listing - NAND configuration structure for free regions of the spare area shows the data type used to specify the contiguous regions of the spare area that are available for the NAND driver to write. The map of the free regions is an array of FS_NAND_FREE_SPARE_DATA values. Each free contiguous section of the spare area will use one index of the array. There must also be a last entry set to {-1, -1} for the driver to know when to stop parsing the table. Note that the factory defect mark should be excluded of the free regions. You can also refer to the example (see Getting Started).

Listing - NAND configuration structure for free regions of the spare area
typedef  struct  fs_nand_free_spare_data {
    FS_NAND_PG_SIZE  OctetOffset;                      (1)
    FS_NAND_PG_SIZE  OctetLen;                         (2)
} FS_NAND_FREE_SPARE_DATA;

(1) Offset (in octets) of a free region.

(2) Length (in octets) of a free region.

ONFI part layer

The ONFI part layer implementation is able to obtain from ONFI compliant devices all the parameters necessary for the NAND driver to operate. The different parameters are extracted from the device parameter page. Table - ONFI parameter page support for different ONFI versions lists the versions of the ONFI standard for which automatic parameter page parsing is supported. If your device does not respect this standard, it should be used with a different implementation of the part layer.

able - ONFI parameter page support for different ONFI versions

ONFI version

Supported parameter page

ONFI 3.0

YES

ONFI 2.3a

YES

ONFI 2.2

YES

ONFI 2.1

YES

ONFI 2.0

YES

ONFI 1.0

YES


The ONFI part layer implementation does not have a lot of configuration options since most parameters are read from the device’s parameter page. The part configuration structure should be initialized to FS_NAND_PartONFI_DfltCfg to ensure upward compatibility with future versions. The configuration fields available for the ONFI part layer implementation are described in Listing - NAND ONFI part layer configuration structure:

Listing - NAND ONFI part layer configuration structure
typedef  struct  fs_nand_part_onfi_cfg {
    FS_NAND_FREE_SPARE_DATA   *FreeSpareMap;               (1)
} FS_NAND_PART_ONFI_CFG;


(1) Pointer to the map of the free regions in the spare area (see listing above).