uC/OS Xilinx SDK Repository Release Notes

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Last updated: Apr 13, 2020 by Former user (Deleted)
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µC/OS Xilinx SDK Repository Release Notes See manual for details.

Version 1.50

Release date: 2020-2-28

  • Open-source Release

Version 1.45

Release date: 2020-1-31

Requirements

  • Xilinx SDK 2019.1

New features & improvements

  • General

    • [712] Standalone updated to v7.0

    • [321] Libmetal updated to V2.0

    • [322] OpenAMP updated to V1.5

    • [296] OpenAMP and Libmetal support added for the Zynq-7000

    • [300] Added OpenAMP and Libmetal demos

    • [725] Improved interoperability with the Xilinx drivers

      • [722][730][731][732] All supported architectures now use the Standalone Library's boot code

      • [715] Replaced custom drivers for the interrupt controllers in favor of the Standalone Xilinx drivers

        • Note: The UCOS_Int API now functions as a wrapper for the Xilinx drivers. Existing ISRs should be updated so their prototypes match the UCOS_INT_FNCT_PTR typedef

    • [736] OS BSPs now make use of the Xilinx timer APIs

    • [737] Updated ISRs in the uC drivers so that they match the new prototype

    • [715] [733] Removed obsolete uC drivers

      • ucos_scugic, ucos_axiintc, ucos_axitimer, ucos_l2cachec, ucos_scuc, ucos_scutimer, ucos_ttcps

Bug Fixes

  • General

    • [818] Fixed errors when generating C++ projects

  • Zynq Ultrascale+

    • [794] Fixed MPU configuration issue in RPU TCP/IP startup code

Version 1.44

Release date: 2019-7-26

Requirements

  • Xilinx SDK 2018.3

New features & improvements

  • General

    • [583] Support for Xilinx SDK 2018.3.
    • [301][490][553] Updated ucos_standalone to standalone v6.8.
      • Note: stdin/stdout under ucos_standalone should now be used to select the UART peripherals.
    • [474][615] BSP configuration options have been revamped to coincide with the latest product releases.
    • [624] Removed the ucos cpu drivers. The Xilinx drivers are now used instead.
  • Zynq Ultrascale+
    • [476] Added TCPIP support for the RPU.

Bug Fixes

  • General

    • [80] XSDK generates an error when creating standalone projects with ucos repo.
    • [255] Tx buffer leak in the GEM driver.
    • [472] Unable to disable Micrium heap through the BSP configuration window.
    • [473] Unable to disable uCOS-III tick task through the BSP configuration window.
      • Note: The tick task was removed in uCOS-III V3.07.
    • [547] axidma driver failed to build with ucos repo.
    • [552] UCOS_TCPIP_PhyCfgInit() chooses incorrect PHY address.
    • [572] ucos_startup.c uses non Thread-Safe print function.
    • [587] AXIUARTLite_RdByte releases the wrong lock.
    • [589] xparameters.h does not populate with fabric interrupts.
    • [599] Zynq-7000 locks on warm-boot.
    • [695] Category headings in the BSP configuration window could be incorrectly configured as booleans.

Version 1.43

Release date: 2018-1-22

Requirements

  • Xilinx SDK 2017.4

New features & improvements

  • General

    • [295] Support for Xilinx SDK 2017.4
    • [221][222] Libmetal and OpenAMP support for uC/OS-III
    • [297] Complete update of software stacks to their latest releases
    • [289] Cleanup of build warnings for the BSPs

  • Zynq Ultrascale+
    • [221][222] Libmetal and OpenAMP support for the RPU
    • [243] Removed unused MMU table from the R5 startup code to save 4KB of memory.

  • Zynq 7000
    • [92] Translation table now uses sections instead of supersections to improve interoperability with the Xilinx MMU functions.

Bug Fixes

  • General

    • [203] Fixed issue with the USB Host MSC demo not allocating enough heap space by default
    • [257] Fixed issue with breakpoints not being recognized in the USB Device driver.
    • [258] Fixed error when cleaning the ucos_standalone component.
    • [262] Fixed issue with CPU_CFG_CACHE_MGMT_EN only being enabled when configured to "auto".
    • [293] Fixed error when generating BSPs for hardware platforms containing cascaded AXI interrupt controllers.
      • Note: Use of AXI interrupt controllers in cascaded mode is not currently supported by the uC/OS repository.

  • Ultrascale+

    • [262] Fixed issue with UCOS_IntSrcDis() having a double CPU_CRITICAL_ENTER().

Version 1.42

Release date: 2017-7-6

Requirements

  • Vivado 2017.2
  • Vivado 2016.4

New features & improvements

  • General

    • DNS demo now waits for the link to go up before resolving the URL.
    • Increased the default stack size for the net TX Dealloc Task to prevent buffer overflows on 64-bit hardware.

  • Zynq Ultrascale+

    • Initial TCPIP support for the A53: GEM controller with 64-bit address space support.
    • Disabled ECC in the R5 startup code to prevent data aborts when using ATCM.
    • Added uC/OS-II port for the A53.
    • Initial XEN support for the A53.

Bug fixes

  • Zynq UltraScale+

    • Fixed the kernel tick frequencies for the A53 and R5.
    • APU Cores 1-3 no longer halt in the startup vector.

Deprecated Features

  • OpenAMP support has been removed for this release due to substantial changes in the source code.

Version 1.41

Release date : 2015-12-22

New features & improvements

  • Zynq UltraScale+ APU (Cortex-A53) : tick source can now be configured between EL1 physical or EL3 physical timers
  • Zynq UltraScale+ APU (Cortex-A53) : Timestamp support in the CPU software module

Requirements

  • Vivado 2015.1

Bug fixes

Zynq-7000 (Cortex-A9)

  • Fixed enumerating FPGA to PS interrupts in Vivado 2015.4

Version 1.40

Release date : 2015-12-07

New features & improvements

  • Support for version 2015.4 of the Xilinx SDK
  • Zynq UltraScale+ MPSoC support for both the APU(Cortex-A53) and RPU(Cortex-R5)

Requirements

  • Vivado 2015.1

Bug fixes

All platforms

  • ucos_axitimer : Fixed usage of the second timer of an AXI Timer block

Version 1.31

Release date : 2015-10-15

New features & improvements

  • Added options to activate the Zynq-7000 instruction and data caches earlier in the startup process to speed up boot time
  • Module initialization can now be disabled on a per module basis
  • New function UCOS_IntTypeSet() to change an interrupt's trigger type
  • Improved OpenAMP support and configuration
  • Added OpenAMP support for the MicroBlaze
  • New USB Host MSC demonstration template
  • Cache support for the MicroBlaze

Requirements

  • Vivado 2015.1

Bug fixes

All platforms

  • Fixed compilation issue when both the USB Host and Device modules are included in a project
  • Fixed spurious interrupts issue when starting from a warm reset 
  • Fixed build compatibility with version 2015.3 of the Xilinx SDK
  • 1.31a Fixed interfaces selection with version 2015.3 of the Xilinx SDK
  • 1.31a Fixed possible race condition in the OpenAMP master demo when running outside of a debugger

Zynq-7000 (Cortex-A9)

  • ucos_axiuartlite: Fixed missing interrupt from an AXI UartLite when accessed from the PS. This issue did not affect a MicroBlaze system
  • ucos_scugic: Fixed issue acknowledging an interrupt generated by another CPU

MicroBlaze

  • Fixed UCOS_Print() and UCOS_Printf() function eternally waiting for an interrupt at startup in some scenarios

Version 1.30

Release date : 2015-07-03

New features & improvements

  • USB support with the addition of the uC/USB-Device and uC/USB-Host software modules
  • CAN connectivity support with the addition of uC/CAN
  • New network modules: MQTT Client, TELNET Server and IPerf
  • Improved AMP support with the addition of the OpenAMP extension

Requirements

  • Vivado 2015.1

Bug fixes

All platforms

  • Fixed a possible linking issue when including the xil library
  • Removed spurious STDIN and STDOUT configuration options from the demo applications

Known Issues

  • The USB Host and CAN modules are not included with the free evaluation available on the website. Please contact Micrium to request an evaluation or to purchase a license
  • The MQTT Client, TELNET Server and IPerf network modules are not included with the free evaluation available on the website. Please contact Micrium to request an evaluation or to purchase a license

Version 1.20

Release date : 2015-05-27

New features & improvements

  • Storage support with the addition of the uC/FS embedded file system
  • Dynamic ticking support for uC/OS-III when running on the Cortex-A9
  • Timestamp support (optional) on the MicroBlaze with the usage of an additional 64 bit AXI Timer

Requirements

  • Vivado 2015.1

Bug fixes

All platforms

  • Fixed compatibility issues with Vivado 2015.1

Zynq-7000 (Cortex-A9)

  • ucos_tcpip: Fixed compilation error when specifying a specific number of DMA descriptors for the Zynq-7000 gigabit Ethernet module
  • ucos_common: Fixed a syntax error in the Makefile when including the CRC feature
  • Fixed logging of peripheral interrupt IDs in the ucos.log file

MicroBlaze

  • Fixed runtime errors when using an AXI Timer with ID higher than 1 as a kernel tick source

Known Issues

  • Compatibility with Vivado versions prior to 2015.1 had to be dropped.
  • A run-time issue may prevent MDIO communication in some scenarios when using the AXI Ethernet Lite. Please contact Micrium if you are experiencing issues with the AXI Ethernet Lite IP.

Version 1.11

Release date : 2015-04-06

New features & improvements

  • N/A

Requirements

  • Vivado 2014.4

Bug fixes

All platforms

  • Fixed compatibility issues when developing in Linux

Zynq-7000 (Cortex-A9)

  • ucos_tcpip: Fixed compilation error when specifying a specific number of DMA descriptors for the Zynq-7000 gigabit Ethernet module
  • ucos_common: Fixed a syntax error in the Makefile when including the CRC feature

Version 1.10

Release date : 2015-03-21

Requirements

  • Vivado 2014.4

New features & improvements

  • Networking support with the uC/TCP-IP protocol stack. Also includes the uC/DNSc and uC/DHCPc DNS and DHCP client applications as well as the uC/HTTPc http client.
  • Ethernet MAC drivers for the Zynq-7000 Gigabit Ethernet and the AXI Ethernet Lite soft IP.
  • AMP configuration support. Allowing the generation of a slave application on the second core of the Zynq-7000.
  • Improved performance and compatibility on the MicroBlaze.
    • MicroBlaze cores without the MSR instruction are now supported.
    • Improved performance on MicroBlaze cores with the pattern comparator.
  • Improved performance on the Cortex-A9 when enabling core specific optimizations.
  • More verbose BSP generation and OS init.
    • A new log called ucos.log is generated along with the BSP to help diagnose configuration issues.
    • When enabled in the BSP global configuration, output messages are generated on the chosen serial interface during init.

Changes

  • Default archiver for Zynq based system switched to the GCC AR driver to support link time optimization (LTO).
  • Many default configurations where modified to make the default values suitable in a wider range of situations.

Bug fixes

All platforms

  • Fixed multiple build warnings when compiling with the -Wall GCC option.

Zynq-7000 (Cortex-A9)

  • Fixed a scripting error when the FIQ/IRQ lines from the PL are used.

MicroBlaze

  • Improved detection of interrupts routed from the PS.

Known Issues

These issues and missing features are known to exist in the current release and are planned to be fixed in a future version. Please contact Micrium if a workaround is needed immediately.

MicroBlaze

  • The BSP generation scripts can't distinguish between multiple AXI Interrupt Controller on the same interconnect.
  • Exceptions are not supported by the BSP.

Version 1.03

Release date : 2015-02-16

Requirements

  • Vivado 2014.4

New features & improvements

  • N/A

Changes

  • N/A

Bug fixes

All platforms

  • N/A

Zynq-7000 (Cortex-A9)

  • Moved initialization of libc after the mmu is enabled to prevent spurious alignment faults. Only affected C++ projects.

MicroBlaze

  • N/A

Known Issues

These issues and missing features are known to exist in the current release and are planned to be fixed in a future version. Please contact Micrium if a workaround is needed immediately.

Zynq-7000 (Cortex-A9)

  • AMP Configuration issue. At this moment, when running uC/OS on both cores require a custom initialization sequence for the second core. Please contact Micrium if you require an AMP configuration.

MicroBlaze

  • The BSP generation scripts can't distinguish between multiple AXI Interrupt Controller on the same interconnect.
  • The MSR instruction is required when configuring the soft processor IP.
  • Exceptions are not supported by the BSP.

Version 1.02

Release date : 2014-01-29

Requirements

  • Vivado 2014.4

New features & improvements

  • A custom handler can be registered for the Cortex-A9 FIQ interrupt signal. This can be done by defining the UCOS_Int_FIQ_Hander() function in user code. Note that usage of the IRQ/FIQ lines from the PL is discouraged when running the Micrium BSP.

Changes

  • ucos_scugic: SCUGICPrioMaskSet() renamed to SCUGIC_PrioMaskSet() to be consistent with the rest of the functions name.

Bug fixes

All platforms

  • ucos_common: Fixed invalid configuration of LIB_MEM_CFG_HEAP_PADDING_ALIGN.
  • ucos_common: Fixed duplicated directories in the built BSP.
  • Fixed compilation errors on Linux.
  • Missing header guards added to the ucos_bsp.h and app_cfg.h header files.
  • ucos_uartps: Added missing parentheses in the UARTPS_WrStr() and UARTPS_WrByte() in the polled write case. This issue could cause some transmit FIFO overflow.
  • Fixed various warnings across the code.

Zynq-7000 (Cortex-A9)

  • ucos_l2cachec: Fixed register definition mistake which prevented the correct initialization of the Zynq L2 cache.
  • Startup code will now skip enabling the caches if the BSP option UCOS_ZYNQ_CONFIG_CACHES is false.

MicroBlaze

  • N/A

Known Issues

These issues and missing features are known to exist in the current release and are planned to be fixed in a future version. Please contact Micrium if a workaround is needed immediately.

Zynq-7000 (Cortex-A9)

  • AMP Configuration issue. At this moment, when running uC/OS on both cores require a custom initialization sequence for the second core. Please contact Micrium if you require an AMP configuration.

MicroBlaze

  • The BSP generation scripts can't distinguish between multiple AXI Interrupt Controller on the same interconnect.
  • The MSR instruction is required when configuring the soft processor IP.
  • Exceptions are not supported by the BSP.

Version 1.01

Release date : 2014-11-11

Requirements

  • Vivado 2014.3

New features & improvements

  • N/A

Changes

  • BSP configuration options STDIN and STDOUT merged into one configuration STDIN_OUT selecting both the input and output UART at the same time

Bug fixes

All platforms

  • ucos_axitimer: Comments header of the function UCOS_START_TASK_PRIO updated to reflect the correct options
  • ucos_uartps: Fixed occasional missing characters when writing a string in interrupt mode
  • Startup task is now correctly using the configuration values UCOS_START_TASK_STACK_SIZE and UCOS_START_TASK_PRIO
  • Configured kernel tick rate now correctly used to configure the tick timer

Zynq-7000 (Cortex-A9)

  • C environment is now correctly initialized
  • MMU translation table could be overwritten in some cases

MicroBlaze

  • Fixed compilation error when leaving the kernel tick source to "none"

Known Issues

These issues and missing features are known to exist in the current release and are planned to be fixed in a future version. Please contact Micrium if a workaround is needed immediately.

Zynq-7000 (Cortex-A9)

  • AMP Configuration issue. At this moment, when running uC/OS on both cores require a custom initialization sequence for the second core. Please contact Micrium if you require an AMP configuration.

MicroBlaze

  • The BSP generation scripts can't distinguish between multiple AXI Interrupt Controller on the same interconnect.
  • The MSR instruction is required when configuring the soft processor IP.
  • Exceptions are not supported by the BSP

Version 1.00

Release date : 2014-10-31

Requirements

  • Vivado 2014.3

New features & improvements

  • Initial release
  • µC/OS-II and µC/OS-III
  • Cortex-A9 and MicroBlaze support

Known Issues

These issues and missing features are known to exist in the current release and are planned to be fixed in a future version. Please contact Micrium if a workaround is needed immediately.

MicroBlaze

  • The BSP generation scripts can't distinguish between multiple AXI Interrupt Controller on the same interconnect
  • The MSR instruction is required when configuring the soft processor IP

Version 1.45

Release date: 2020-1-31

Requirements

·         Xilinx SDK 2019.1

New features & improvements

·         General

  • [712] Standalone updated to v7.0
  • [321] Libmetal updated to V2.0
  • [322] OpenAMP updated to V1.5
  • [296] OpenAMP and Libmetal support added for the Zynq-7000
  • [300] Added OpenAMP and Libmetal demos
  • [725] Improved interoperability with the Xilinx drivers
    • [722][730][731][732] All supported architectures now use the Standalone Library's boot code
    • [715] Replaced custom drivers for the interrupt controllers in favor of the Standalone Xilinx drivers
      • Note: The UCOS_Int API now functions as a wrapper for the Xilinx drivers. Existing ISRs should be updated so their prototypes match the UCOS_INT_FNCT_PTR typedef
  • [736] OS BSPs now make use of the Xilinx timer APIs
  • [737] Updated ISRs in the uC drivers so that they match the new prototype
  • [715] [733] Removed obsolete uC drivers
    • ucos_scugic, ucos_axiintc, ucos_axitimer, ucos_l2cachec, ucos_scuc, ucos_scutimer, ucos_ttcps

Bug Fixes

·         General

·         [818] Fixed errors when generating C++ projects

·         Zynq Ultrascale+ 

·         [794] Fixed MPU configuration issue in RPU TCP/IP startup