When setting OS_CFG_ISR_POST_DEFERRED_EN to 0, µC/OS-III will disable interrupts before entering a critical section and re-enable them when leaving the critical section.
OS_CRITICAL_ENTER() invokes the µC/CPU macro CPU_CRITICAL_ENTER() that, in turn, calls CPU_SR_Save(). CPU_SR_Save() is a function typically written in assembly language that saves the current interrupt disable status and then disables interrupts. The saved interrupt disable status is returned to the caller and in fact, it is stored onto the caller’s stack in a variable called “cpu_sr”.
OS_CRITICAL_EXIT() and OS_CRITICAL_EXIT_NO_SCHED() both invoke the µC/CPU macro CPU_CRITICAL_EXIT(), which maps to CPU_SR_Restore(). CPU_SR_Restore() is passed the value of the saved “cpu_sr” variable to re-establish interrupts the way they were prior to calling OS_CRITICAL_ENTER().
The typical code for the macros is shown in Listing 4-1.