The NAND driver comprises multiple layers, as depicted in Figure 15 - 1. 
NAND driver architecture.
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The generic NAND translation layer provides sector abstraction and performs wear-leveling (to ensure all blocks are used equally).
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The controller layer driver interfaces with the NAND translation layer at the physical level (block erase, sector write/read, spare area write/read operations). The controller layer is also responsible for the placement of sectors and metadata within a NAND page. Interfacing at this level allows more flexibility: if your micro-controller has dedicated hardware like an ECC calculation engine or a NAND flash memory controller, you can interface directly with it by providing your own controller layer implementation instead of using the generic implementation (see section 15-4-1 “Generic Generic Controller Layer Implementation”Implementation) included with the NAND driver.
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