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typedef struct fs_dev_nor_cfg {

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    CPU_ADDR            AddrBase;

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    CPU_INT08U          RegionNbr;

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    CPU_ADDR            AddrStart;

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    CPU_INT32U          DevSize;

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    FS_SEC_SIZE         SecSize;

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    CPU_INT08U          PctRsvd;

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    CPU_INT16U          EraseCntDiffTh;

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    FS_DEV_NOR_PHY_API *PhyPtr;

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    CPU_INT08U          BusWidth;

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    CPU_INT08U          BusWidthMax;

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    CPU_INT08U          PhyDevCnt;

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    CPU_INT32U          MaxClkFreq;

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  } FS_DEV_NOR_CFG;

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File
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Used for
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fs_dev_nor.h
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Second argument of FSDev_Open() (when opening a NOR device)
 Anchor10952141095214Configures the properties of a NOR device that will be opened. A pointer to this structure is passed as the second argument of FSDev_Open() for a NOR device.anchor10952151095215
Members
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AddrBase Anchor10991911099191
must specify
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1. the base address of the NOR flash memory, for a parallel NOR.
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2. 0x00000000 for a serial NOR.
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RegionNbr Anchor10991941099194
must specify the block region which will be used for the file system area. Block regions are enumerated by the physical-layer driver; for more information, see the physical-layer driver header file. (on monolithic devices, devices with only one block region, this must be 0).
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10952201095220AddrStart Anchor10991951099195
must specify
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1. the absolute start address of the file system area in the NOR flash memory, for a paralel NOR.
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2. the offset of the start of the file system in the NOR flash, for a serial NOR.
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The address specified by AddrStart must lie within the region RegionNbr.
 Anchor10952241095224DevSize Anchor10991991099199
must specify the number of octets that will belong to the file system area.
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SecSize Anchor10992001099200
must specify the sector size for the NOR flash (either 512, 1024, 2048 or 4096).
 Anchor10952261095226PctRsvd Anchor10992011099201
must specify the percentage of sectors on the NOR flash that will be reserved for extra-file system storage (to improve efficiency). This value must be between 5% and 35%, except if 0 is specified whereupon the default will be used (10%).
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EraseCntDiffTh Anchor10992021099202
must specify the difference between minimum and maximum erase counts that will trigger passive wear-leveling. This value must be between 5 and 100, except if 0 is specified whereupon the default will be used (20).
 Anchor10952281095228PhyPtranchor10992031099203
must point to the appropriate physical-layer driver:
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class
WebWorks_Indent_1
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FSDev_NOR_AMD_1x08
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class
WebWorks_Indent_2
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CFI-compatible parallel NOR implementing AMD command set, 8-bit data bus.
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FSDev_NOR_AMD_1x16
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class
WebWorks_Indent_2
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CFI-compatible parallel NOR implementing AMD command set, 16-bit data bus.
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class
WebWorks_Indent_1
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FSDev_NOR_Intel_1x16
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CFI-compatible parallel NOR implementing Intel command set, 16-bit data bus
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class
WebWorks_Indent_1
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FSDev_NOR_SST39
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class
WebWorks_Indent_2
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SST SST39 Multi-Purpose Flash
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FSDev_NOR_STM25
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class
WebWorks_Indent_2
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ST M25 serial flash
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class
WebWorks_Indent_1
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FSDev_NOR_SST25
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class
WebWorks_Indent_2
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SST SST25 serial flash
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Other
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User-developed
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For a parallel NOR, the bus configuration is specified via BusWidth, BusWidthMax and PhyDevCnt:
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BusWidthanchor10992121099212
is the bus width, in bits, between the MCU/MPU and each connected device.
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1095238BusWidthMax Anchor10992131099213
is the maximum width supported by each connected device.
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PhyDevCntanchor10992141099214
is the number of devices interleaved on the bus.
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For a serial flash, the maximum clock frequency is specified via MaxClkFreq.
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Notes
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None.