SPI is a simple protocol supported by peripherals commonly built-in on CPUs. Moreover, since the communication can easily be accomplished by software control of GPIO pins (“software SPI” or “bit-banging”), a SD/MMC card can be connected to almost any platform. In SPI mode, seven pins on the SD/MMC device are used, with the functions listed in Table 14-4. As with any SPI device, four signals are used to communicate with the host (CS, DataIn, CLK and DataOut). Some card holders contain circuitry for card detect and write protect indicators, which the MCU/MPU may also monitor.
Pin | Name | Type | Description |
1 | CS | I | Chip Select |
2 | DataIn | I | Host-to-card commands and data |
3 | Vss1 | S | Supply voltage ground |
4 | VDD | S | Supply voltage |
5 | CLK | I | Clock |
6 | VSS2 | S | Supply voltage ground |
7 | DataOut | O | Card-to-host data and status |
Table 14-4 SD/MMC pinout (SPI mode)
The four signals connecting the host (or master) and card (also known as the slave) are named variously in different manuals and documents. The DataIn pin of the card is also known as MOSI (Master Out Slave In); it is the data output of the host CPU. Similarly, the DataOut pin of the card is also known as MISO (Master In Slave Out); it is the data input of the host CPU. The CS and CLK pins (also known as SSEL and SCK) are the chip select and clock pins. The host selects the slave by asserting CS, potentially allowing it to choose a single peripheral among several that are sharing the bus (i.e., by sharing the CLK, MOSI and MISO signals).
When a card is first connected to the host (at card power-on), it is in the ‘inactive’ state, awaiting a GO_IDLE_STATE command to start the initialization process. The card will enter SPI mode (rather than card mode) because the driver holds the CS signal low while executing the GO_IDLE_STATE command. The card now in the ‘idle’ state moves through the ‘ready’ (as long as it supports the voltage range specified by the host) before ending up in ‘standby’. It can now get selected by the host (using the chip select) for data transfers. Figure 15-5 flowcharts this procedure.