Architecture Overview

Architecture Overview

The NAND driver comprises multiple layers, as depicted in Figure 13-1.

1. 1. NAND driver architecture

The generic NAND translation layer provides sector abstraction and performs wear-leveling (to ensure all blocks are used equally).

The controller layer driver interfaces with the NAND translation layer at the physical level (block erase, sector write/read, spare area write/read operations). The controller layer is also responsible for the placement of sectors and metadata within a NAND page. Interfacing at this level allows more flexibility: if your micro-controller has dedicated hardware like an ECC calculation engine or a NAND flash memory controller, you can interface directly with it by providing your own controller layer implementation instead of using the generic implementation (see section 13-4-1 “Generic Controller Layer Implementation” on page 181) included with the NAND driver.

The controller extension layer is specific to the generic controller implementation (fs_dev_nand_ctrlr_gen.*). It provides an interface that allows different types of ECC calculation and correction schemes to be used while avoiding duplication of the generic controller code. Implementations for software ECC and some Micron on-chip ECC devices (including MT29F1G08ABADA) are provided with the NAND flash driver.

The BSP layer will implement code that depends on your platform and application for the specific controller layer implementation chosen. In most cases, you will need to develop your own implementation of the BSP layer.

The part layer is meant to provide the specifics for each part/chip you use in your design to the controller and NAND translation layers. This layer implementation will typically be chosen from the implementations included with the NAND driver. This implementation can either rely on statically defined parameters or values read directly from the device (for an ONFI compliant part).

The ECC layer provides code calculation and error correction functions. For performance reasons, only a 1-bit ECC software module based on Hamming codes is provided (part of the µC/CRC product bundled with µC/FS). If a more robust ECC correction scheme is required, it is strongly recommended to use hardware engines. Since the ECC-specific code of the generic controller driver is implemented in generic controller extension modules, it can easily be adapted if the micro-controller or NAND flash device can handle ECC automatically.