Configuration
Default MMU configuration
To simplify development the BSP pre-configure the memory manager with a simple 1:1 memory map. The entire peripheral memory range, including the on chip ram is mapped as device memory while the external DDR is mapped as cacheable normal memory.
Default cache configuration
The L1 and L2 cache are enable by default when initializing the BSP.
Overriding the default initialization sequence
In the ZYNQ section of the BSP settings various initialization steps can be disabled if desired.
| Configuration | Description |
|---|
| ZYNQ_CONFIG_MMU | Configure the MMU with a default page table but leave it disabled | | ZYNQ_ENABLE_MMU | Enable the MMU after configuration. This also enable the SCU and instruct the current core to join SMP | | ZYNQ_CONFIG_CACHES | Configure the caches but leave them disabled | | ZYNQ_ENABLE_CACHES | Enable the L1 and L2 caches | | ZYNQ_ENABLE_PERF_OPTIMS | Enable various hardware performance optimizations unique to the Cortex-A9 core |
|
Kernel tick source
The kernel timebase on the Cortex-A9 is always derived from the core's private timer.