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Limitations

The uC/OS BSP currently has the following limitations with respect to the configuration of a MicroBlaze system :

  • MSR Instruction must be included
  • Exceptions are not supported

Additionally the AXI Interrupt Controller configuration has the following limitations :

  • Fast Interrupts and cascaded operation are not supported
  • IPR register must be included
  • Multiple AXI Interrupt controller on the same interconnect will confuse the BSP generator

Interrupt handling

The uC/OS BSP supports the AXI Interrupt Controller to provide a MicroBlaze system with multiple independent interrupt lines. The interrupt controller can be left out, in which case the interrupt handling code acts as one source controller.

Most interrupt signal from the peripherals available in the Vivado IP Integrator have a different polarity with respect to the MicroBlaze raw interrupt input.

Kernel tick source

For the MicroBlaze the source of the kernel timebase can be selected among the timers available in the hardware.

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