Page Comparison

V2.93.01

Release Date

May 5th, 2021

Bug Fixes

• Fix to the ARMv7-M port: Interrupts are disabled before modifying BASEPRI as per Cortex-M7 errata

V2.93.00

Release Date

February 28th, 2020

• Open-source Release

V2.92.18

Release Date

December 17th, 2019

New Features

[613] Added TLS support for EWARM 8: uCOS-II/TLS/IAR/os_tls_v8.c

Bug Fixes

[632] Fixed a race condition which occurs if a task using multipend is signaled by a post and has its priority increased before it has a chance to run.

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[618] Removed duplicate initialization of OS globals from the C28x port

V2.92.17

Release Date

September 20th, 2019

Bug Fixes

• [17434] Removed obsolete references to APP_CFG_PROVE_OS_PLUGIN_EN from the Configuration templates

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• [17341] Static analysis fixes
  
  • "Include guard" warnings for ucos_ii.c and os.h
  • "unused variable" warning in os_core.c
  • "bitwise operand with different sizes"  in os_mutex.c

V2.92.16

Release Date

March 21, 2019

New Features

• [425] ARMv7-M Non-Kernel-Aware Interrupt support

Bug Fixes

• [28] C28x port overwrote the value of IER if an interrupt-level context switch occurred.

V2.92.15

Release Date

June 18, 2018

New Features

• [361] Added MPC57xx-VLE port
• [240] Added trace support to the Cortex-A port
  

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• [154] ARM port directories have been restructured and consolidated (e.g. ARM-Cortex-A/ARMv7-A, ARM-Cortex-A/ARMv8-A)
• [312] Removed unused parameter warnings in OSTaskStkInit() for the ARMv7-A and ARMv8-A ports
• [211] Removed superfluous OS_BSP_TickInit() and OS_BSP_TickISR() prototypes from the Renesas RX ports

Bug Fixes

• [260] RL78 port should use RETB instead of RETI for software breaks
• [314] Microblaze port is missing function declarations in the header
• [358] In OS_TaskStat(), the calculation for OSCPUUsage may be negative
• [359] In OS_TaskStat(), OSCPUUsage may be not equal to zero even if no other tasks are running

V2.92.14

Release Date

December 8, 2017

New Features

• [200] Added a new port for the RISC-V architecture

Bug Fixes

• [259] Cortex-A50 port used improper data width when writing to OSRunning.

V2.92.13

Release Date

August 17, 2017

New Features

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• [176] Removed ARM-Cortex-A8 port (Replaced by ARM-Cortex-A).
• [176] Removed ARM-Cortex-A9 port (Replaced by ARM-Cortex-A).
• [176] Removed ARM-Cortex-R4 port (Replaced by ARM-Cortex-A).
• [176] Removed ARM-Cortex-M3 port (Replaced by ARM-Cortex-M).
• [176] Removed ARM-Cortex-M4 port (Replaced by ARM-Cortex-M).
• [176] Removed RX-FPU port (Replaced by ARM-Cortex-RX).
• [176] Removed RX200 port (Replaced by ARM-Cortex-RX).
• [176] Removed RX600 port (Replaced by ARM-Cortex-RX).
• [176] Removed RX610 port (Replaced by ARM-Cortex-RX).
• [176] Removed RX62N port (Replaced by ARM-Cortex-RX).

V2.92.12

Release Date

May 25, 2016

New Features & Improvements

• ARM-Cortex-M Port: Added Generic port forARMCortex-M3,M4andM7devices.
• ARM-Cortex-M0 Port: Added support for ARM Cortex-M0+ devices.
• MSP430x Port: Added CCS toolchain support for MSP430x5xx devices.
• RL78 Port: Added GNURL78 toolchain support.
• TI C2000 (C28x) Port: Added support for Piccolo and Delfino devices.

Bug Fixes

• Core: OSSafetyCritical Flag now checked in all OS???Create() and OS???Del() functions.

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Thread Local Storage (TLS) allows each task to have task specific variables that are typically required by compilers and their run-time library.  TLS is optional and only currently available for a couple of compilers (CCES from Analog Devices and Embedded Workbench from IAR).  TLS requires that you enable this feature by setting the TLS table size (see the MicroC/OS-II user’s manual) through the #define OS_TLS_TBL_SIZE and, if defined, must be greater than 0.

TLS is mandatory if you use non-reentrant library functions that are not protected by either a mutex or a semaphore. Forexamplethe‘strtok()’ function needs to keep a copy of a pointer forfurtherinvocationsofstrtok().  This local pointer is now saved as part of the TLS management when TLS is enabled and thus does not require that you protect the non-reentrant code with a mutex or a semaphore. 

1)  A number of ‘internal’ functions have been added to support TLS.  However, as the user, you only need to:

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Added OSTaskRegGetID() to dynamically assign task IDs instead of assigning task IDs statically through #define constants.  It’s important that you either use ‘dynamic task register ID allocation’ or ‘static register ID allocation’ but not both.  The preferred method is to use OSTaskRegGetID() throughout your code.

You now need to allocate an INT8U variable for each task register IDs and use those variables to specify the desired task register.  In other words: 

INT8U  MyTaskRegID;

:

:

    MyTaskRegID = OSTaskRegGetID(&err);

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            The new value of these #defines are either 0 (to disable naming the object) or 1 (to enable naming the object).

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            Added support for multi-pend.   

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