...
The uC/OS BSP currently has the following limitations with respect to the configuration of a MicroBlaze system :
- MSR Instruction must be included
- Exceptions are not supported
Additionally usage of the AXI Interrupt Controller configuration has the following limitations :
- Fast Interrupts and cascaded operation are not supported
- IPR register must be included
- Multiple AXI Interrupt controller on the same interconnect will confuse the BSP generator
Interrupt handling
The uC/OS BSP supports the AXI Interrupt Controller to provide a MicroBlaze system with multiple independent interrupt lines. The interrupt controller can be left out, in which case the interrupt handling code acts as one source controller.
| Note |
|---|
Most interrupt signal from the peripherals available in the Vivado IP Integrator have a different polarity with respect to the MicroBlaze raw interrupt input. |
Kernel tick source
For the MicroBlaze the source of the kernel timebase can be selected among the timers available in the hardwareThe kernel timebase on a MicroBlaze system can be derived from any available AXI Timer available in the hardware. It's also possible to reduce resource usage by using a fixed interval timer, or any other periodic interrupt source. The tick source can be configured by setting the MB_KERNEL_TICK_SRC configuration in the BSP settings. When using a fixed source the attached interrupt controller should be selected and the interrupt source configured in MB_KERNEL_TICK_INT_SRC.
No kernel tick
For absolute minimum resource usage it's possible to run the kernel without a timebase. Timeouts, delays and software timers will not work in this configuration.
MicroBlaze hardware design
Most configurations of the MicroBlaze are support to suit a design's needs. However the MSR instruction and pattern comparator option will give a considerable boost in kernel performance at a minimal logic resource cost.