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In the ZYNQ section of the BSP settings various initialization steps can be disabled if desired.
Configuration | Description |
|---|---|
| ZYNQ_CONFIG_MMU | Configure the MMU with a default page table but leave it disabled |
| ZYNQ_ENABLE_MMU | Enable the MMU after configuration. This also enable the SCU and instruct the current core to join SMP |
| ZYNQ_CONFIG_CACHES | Configure the caches but leave them disabled |
| ZYNQ_ENABLE_CACHES | Enable the L1 and L2 caches |
| ZYNQ_ENABLE_PERF_OPTIMS | Enable various hardware performance optimizations unique to the Cortex-A9 core |
Table - Cortex-A9 Init Configuration
Kernel tick source
The kernel timebase on the Cortex-A9 is always derived from the core's private timer.
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