µC/OS Xilinx SDK Repository Release Notes See manual for details.
| Table of Contents | ||||||
|---|---|---|---|---|---|---|
|
Version 1.50
Release date: 2020-2-28
- Open-source Release
Version 1.45
Release date: 2020-1-31
...
New features & improvements
General
[712] Standalone updated to v7.0
[321] Libmetal updated to V2.0
[322] OpenAMP updated to V1.5
[296] OpenAMP and Libmetal support added for the Zynq-7000
[300] Added OpenAMP and Libmetal demos
[725] Improved interoperability with the Xilinx drivers
[722][730][731][732] All supported architectures now use the Standalone Library's boot code
[715] Replaced custom drivers for the interrupt controllers in favor of the Standalone Xilinx drivers
Note: The UCOS_Int API now functions as a wrapper for the Xilinx drivers. Existing ISRs should be updated so their prototypes match the UCOS_INT_FNCT_PTR typedef
[736] OS BSPs now make use of the Xilinx timer APIs
[737] Updated ISRs in the uC drivers so that they match the new prototype
[715] [733] Removed obsolete uC drivers
ucos_scugic, ucos_axiintc, ucos_axitimer, ucos_l2cachec, ucos_scuc, ucos_scutimer, ucos_ttcps
...
Bug Fixes
General
[818] Fixed errors when generating C++ projects
Zynq Ultrascale+
[794] Fixed MPU configuration issue in RPU TCP/IP startup code
Version 1.44
Release date: 2019-7-26
...
New features & improvements
General
- [583] Support for Xilinx SDK 2018.3.
- [301][490][553] Updated ucos_standalone to standalone v6.8.
- Note: stdin/stdout under ucos_standalone should now be used to select the UART peripherals.
- [474][615] BSP configuration options have been revamped to coincide with the latest product releases.
- [624] Removed the ucos cpu drivers. The Xilinx drivers are now used instead.
- Zynq Ultrascale+
- [476] Added TCPIP support for the RPU.
Bug Fixes
General
- [80] XSDK generates an error when creating standalone projects with ucos repo.
- [255] Tx buffer leak in the GEM driver.
- [472] Unable to disable Micrium heap through the BSP configuration window.
- [473] Unable to disable uCOS-III tick task through the BSP configuration window.
- Note: The tick task was removed in uCOS-III V3.07.
- [547] axidma driver failed to build with ucos repo.
- [552] UCOS_TCPIP_PhyCfgInit() chooses incorrect PHY address.
- [572] ucos_startup.c uses non Thread-Safe print function.
- [587] AXIUARTLite_RdByte releases the wrong lock.
- [589] xparameters.h does not populate with fabric interrupts.
- [599] Zynq-7000 locks on warm-boot.
- [695] Category headings in the BSP configuration window could be incorrectly configured as booleans.
...
New features & improvements
General
- [295] Support for Xilinx SDK 2017.4
- [221][222] Libmetal and OpenAMP support for uC/OS-III
- [297] Complete update of software stacks to their latest releases
- [289] Cleanup of build warnings for the BSPs
- Zynq Ultrascale+
- [221][222] Libmetal and OpenAMP support for the RPU
- [243] Removed unused MMU table from the R5 startup code to save 4KB of memory.
- Zynq 7000
- [92] Translation table now uses sections instead of supersections to improve interoperability with the Xilinx MMU functions.
Bug Fixes
General
- [203] Fixed issue with the USB Host MSC demo not allocating enough heap space by default
- [257] Fixed issue with breakpoints not being recognized in the USB Device driver.
- [258] Fixed error when cleaning the ucos_standalone component.
- [262] Fixed issue with CPU_CFG_CACHE_MGMT_EN only being enabled when configured to "auto".
- [293] Fixed error when generating BSPs for hardware platforms containing cascaded AXI interrupt controllers.
- Note: Use of AXI interrupt controllers in cascaded mode is not currently supported by the uC/OS repository.
Ultrascale+
- [262] Fixed issue with UCOS_IntSrcDis() having a double CPU_CRITICAL_ENTER().
...
New features & improvements
General
- DNS demo now waits for the link to go up before resolving the URL.
- Increased the default stack size for the net TX Dealloc Task to prevent buffer overflows on 64-bit hardware.
Zynq Ultrascale+
- Initial TCPIP support for the A53: GEM controller with 64-bit address space support.
- Disabled ECC in the R5 startup code to prevent data aborts when using ATCM.
- Added uC/OS-II port for the A53.
- Initial XEN support for the A53.
...
- The BSP generation scripts can't distinguish between multiple AXI Interrupt Controller on the same interconnect
- The MSR instruction is required when configuring the soft processor IP
Version 1.45
Release date: 2020-1-31
Requirements
· Xilinx SDK 2019.1
New features & improvements
· General
- [712] Standalone updated to v7.0
- [321] Libmetal updated to V2.0
- [322] OpenAMP updated to V1.5
- [296] OpenAMP and Libmetal support added for the Zynq-7000
- [300] Added OpenAMP and Libmetal demos
- [725] Improved interoperability with the Xilinx drivers
- [722][730][731][732] All supported architectures now use the Standalone Library's boot code
- [715] Replaced custom drivers for the interrupt controllers in favor of the Standalone Xilinx drivers
- Note: The UCOS_Int API now functions as a wrapper for the Xilinx drivers. Existing ISRs should be updated so their prototypes match the UCOS_INT_FNCT_PTR typedef
- [736] OS BSPs now make use of the Xilinx timer APIs
- [737] Updated ISRs in the uC drivers so that they match the new prototype
- [715] [733] Removed obsolete uC drivers
- ucos_scugic, ucos_axiintc, ucos_axitimer, ucos_l2cachec, ucos_scuc, ucos_scutimer, ucos_ttcps
Bug Fixes
· General
· [818] Fixed errors when generating C++ projects
· Zynq Ultrascale+
· [794] Fixed MPU configuration issue in RPU TCP/IP startup