µC/OS-III handles event posting from interrupts using two different methods: Direct and Deferred Post. These will be discussed in greater detail in Interrupt Management. From a scheduling point of view, the end result of the two methods is the same; the highest priority ready task will receive the CPU as shown in the figures below.
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(1) A low priority task is executing, and an interrupt occurs. (2) If interrupts are enabled, the CPU vectors (i.e., jumps) to the ISR that is responsible for servicing the interrupting device. (3) The ISR services the device and signals or sends a message to a higher-priority task waiting to service this device. This task is thus ready-to-run. (4) When the ISR completes its work it makes a service call to µC/OS-III. (5) (6) Since there is a more important ready-to-run task, µC/OS-III decides to not return to the interrupted task but switches to the more important task. See Context Switching for details on how this works. (7) (8) The higher priority task services the interrupting device and, when finished, calls µC/OS-III asking it to wait for another interrupt from the device. (9) (10) µC/OS-III blocks the high-priority task until the next time the device needs servicing. Since the device has not interrupted a second time, µC/OS-III switches back to the original task (the one that was interrupted). (11) The interrupted task resumes execution, exactly at the point where it was interrupted. |