The NAND translation layer is the main layer of the driver, implemented by the files fs_dev_nand.c and fs_dev_nand.h. This layer contains most of the algorithms necessary to overcome the following limitations of NAND flash technology:
- Write operations can only change a bit state from ‘1’ to ‘0’. Only erase operations can revert the bit state, from ‘0’ to ‘1’.
- Erase operations are only performed on large sections of the memory called blocks (typically between 16 kB and 512 kB).
- Write operations are performed on a sub-section of a block, called a page (typically between 512 and 8192 octets).
- Some devices support partial page programming (splitting the operation to write a full page into multiple operations that each write a sub-section of the page). Other devices can only have their pages written in a single operation before they are erased.
- Some devices must write the pages of a block in a sequential manner (page 0, page 1, page 2, etc.).
- Blocks can only be erased a limited number of times (typically 10k to 100k) before the integrity of the memory is compromised.
- Some device blocks can’t be used reliably and are considered bad blocks. These blocks are either marked at the factory or become bad during the device’s life.
- Electric disturbance can cause read errors. An error correction mechanism must be used to decrease the bit error rate.
The role of the translation layer is to translate those NAND flash specific requirements into a disk interface, based on sector access. This disk interface allows the NAND driver to be used with traditional sector-based file systems like FAT, which is used by µC/FS.
The translation layer implementation provided with the NAND driver is inspired by the KAST (K-Associative Sector Translation) as proposed by Cho (see Appendix G, “Bibliography” Bibliography).
In the provided implementation, three types of blocks are present on the device. The data blocks typically occupy the major portion of the storage space. Data blocks are used to contain the data written to the device by the application or file system. A mapping between the logical addresses of the blocks and their physical locations is used to enable wear-leveling.
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In this implementation, it is possible to specify how many different data blocks pointed to by a single update block. This specification is called maximum associativity (see the configuration field .RUB_MaxAssoc in section “Device configuration” Translation Layer Configuration). If this value is greater than one, the merge operation must be performed for each data block associated with the update block being folded.
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