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Anchor10466331046633 SD/MMC CardMode Communication Anchor10466341046634In card mode, seven, nine or thirteen pins on the SD/MMC device are used, with the functions listed in the table below. All cards start up in “1 bit” mode (upon entering identification mode), which involves only a single data line. Once the host (the MCU/MPU) discovers the capabilities of the card, it may initiate 4- or 8-bit communication (the latter available only on new MMCs). Some card holders contain circuitry for card detect and write protect indicators, which the MCU/MPU may also monitor.anchor

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Pin Name Type Description 1 CD/DAT3 I/O1049042
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Table Cell (td)
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Table Cell (td)
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Table Cell (td)
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Table Cell (td)
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1049044
titleTable - SD/MMC pinout (Card mode)


Pin

Name

Type

Description

1

CD/DAT3

I/O

Card Detect/Data Line (Bit 3)

Table Row (tr)
Table Cell (td)
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1049044

2

Table Cell (td) Anchor10490461049046

CMD

Table Cell (td)anchor1049048

1049048

I/O

td

Anchor10490501049050

Command/Response

Table Row (tr) Table Cell (td) Anchor10490521049052

3

Table Cell (td) Anchor10490541049054

Vss1

Table Cell (td) Anchor1049056

1049056

S

Table Cell (td) Anchor10490581049058

Supply voltage ground

tr

Table Cell (td) Anchor10490601049060

4

Table Cell (td) Anchor10490621049062

VDD

Table Cell (td) Anchor10490641049064

S

Table Cell (td) Anchor10490661049066

Supply voltage

tr

Table Cell (td) Anchor10490681049068

5

Table Cell (td)anchor1049070

1049070

CLK

td

Anchor10490721049072

I

Table Cell (td) Anchor10490741049074

Clock

Table Row (tr) Table Cell (td) Anchor10490761049076

6

Table Cell (td) Anchor1049078

1049078

VSS2

Table Cell (td) Anchor10490801049080

S

td

Anchor10490821049082

Supply voltage ground

Table Row (tr) Table Cell (td) Anchor10490841049084

7

Table Cell (td) Anchor10490861049086

DAT0

Table Cell (td) Anchor10490881049088

I/O

td

Anchor10490901049090

Data Line (Bit 0)

Table Row (tr) Table Cell (td)anchor1049092

1049092

8

td

Anchor10490941049094

DAT1

Table Cell (td) Anchor10490961049096

I/O

Table Cell (td) Anchor10490981049098

Data Line (Bit 1)

Table Row (tr) Table Cell (td) Anchor1049100

1049100

9

Table Cell (td) Anchor10491021049102

DAT2

td

Anchor10491041049104

I/O

Table Cell (td) Anchor10491061049106

Data Line (Bit 2)

Table Row (tr) Table Cell (td) Anchor10491081049108

10

Table Cell (td) Anchor10491101049110

DAT4

td

Anchor10491121049112

I/O

Table Cell (td) Anchor1049114

1049114

Data Line (Bit 4)*

Table Row (tr) Table Cell (td) Anchor10491161049116

11

Table Cell (td) Anchor10491181049118

DAT5

Table Cell (td) Anchor10491201049120

I/O

Table Cell (td) Anchor10491221049122

Data Line (Bit 5)*

Table Row (tr) Table Cell (td) Anchor10491241049124

12

td

Anchor10491261049126

DAT6

Table Cell (td) Anchor10491281049128

I/O

Table Cell (td) Anchor10491301049130

Data Line (Bit 6)*

Table Row (tr) Table Cell (td) Anchor10491321049132

13

td

Anchor10491341049134

DAT7

Table Cell (td) Anchor1049136

1049136

I/O

Table Cell (td) Anchor10491381049138

Data Line (Bit 7

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Anchor10466511046651Exchanges between the host and card begin with a command (sent by the host on the CMD line), often followed by a response from the card (also on the CMD line); finally, one or more blocks data may be sent in one direction (on the data line(s)), each appended with a CRC.anchor

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titleFigure - SD/MMC communication sequence

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(1) When no data is being transmitted, data lines are held low.

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(2) Data block is preceded by a start bit (‘0’); an end bit (‘1’) follows the CRC.

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(3) The CRC is the 16-bit CCITT CRC.

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(4) During the busy signaling following a write, DAT0 only is held low.

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(5) See Figure - SD/MMC command and response formats for description of the command format.

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(6) See Figure - SD/MMC command and response formats for description of the command format.

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titleFigure - SD/MMC command and response formats

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(1) Command index is not valid for response formats R2 and R3.

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(2) CRC is not valid for response format R3.

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When a card is first connected to the host (at card power-on), it is in the ‘inactive’ state, awaiting a GO_IDLE_STATE command to start the initialization process, which is dependent on the card type. During initialization, the card starting in the ‘idle’ state moves through the ‘ready’ (as long as it supports the voltage range specified by the host) and ‘identification’ states (if it is assigned an address by or is assigned an address) before ending up in ‘standby’. It can now get selected by the host for data transfers. Figure 15-9 - Simplified SD/MMC cardmode initialization and state transitions flowcharts this procedure.