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Context switching adds overhead. The more registers a CPU has, the higher the overhead. The time required to perform a context switch is generally determined by how many registers must be saved and restored by the CPU.
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os_cpu.h
, os_cpu_c.c
and os_cpu_a.asm
. Chapter 18Chapter 18, “Porting µC/OS-III” on page 335 provides more details on the steps needed to port µC/OS-III to different CPU architectures.anchorIn this chapter, we will discuss the context switching process in generic terms using a fictitious CPU as shown in Figure 8 Figure 8-1. Our fictitious CPU contains 16 integer registers (R0 to R15), a separate ISR stack pointer, and a separate status register (SR). Every register is 32 bits wide and each of the 16 integer registers can hold either data or an address. The program counter (or instruction pointer) is R15 and there are two separate stack pointers labeled R14 and R14’. R14 represents a task stack pointer (TSP), and R14’ represents an ISR stack pointer (ISP). The CPU automatically switches to the ISR stack when servicing an exception or interrupt. The task stack is accessible from an ISR (i.e., we can push and pop elements onto the task stack when in an ISR), and the interrupt stack is also accessible from a task. Anchor
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Figure 8-1 Fictitious CPU
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The task stack pointer points to the last register saved onto the task’s stack. The program counter (PC
or R15
) and status register (SR
) are the first registers saved onto the stack. In fact, these are saved automatically by the CPU when an exception or interrupt occurs (assuming interrupts are enabled) while the other registers are pushed onto the stack by software in the exception handler. The stack pointer (SP
or R14
) is not actually saved on the stack but instead is saved in the task’s OS_TCB
. 1042717 Anchor
The interrupt stack pointer points to the current top-of-stack for the interrupt stack, which is a different memory area. When an ISR executes, the processor uses R14’ as the stack pointer for function calls and local arguments. Anchor
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Figure 8-2 CPU register stacking order of ready task
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OSCtxSw()
, which is actually invoked by the macro OS_TASK_SW()
. A macro is used as there are many ways to invoke OSCtxSw()
such as software interrupts, trap instructions, or simply calling the function. The ISR context switch is implemented by OSIntCtxSw()
. The code for both functions is typically written in assembly language and is found in a file called os_cpu_a.asm
.