µC/OS Xilinx SDK Repository Release Notes See manual for details.
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Version 1.50
Release date: 2020-2-28
- Open-source Release
Version 1.45
Release date: 2020-1-31
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- The BSP generation scripts can't distinguish between multiple AXI Interrupt Controller on the same interconnect
- The MSR instruction is required when configuring the soft processor IP
Version 1.45
Release date: 2020-1-31
Requirements
· Xilinx SDK 2019.1
New features & improvements
· General
- [712] Standalone updated to v7.0
- [321] Libmetal updated to V2.0
- [322] OpenAMP updated to V1.5
- [296] OpenAMP and Libmetal support added for the Zynq-7000
- [300] Added OpenAMP and Libmetal demos
- [725] Improved interoperability with the Xilinx drivers
- [722][730][731][732] All supported architectures now use the Standalone Library's boot code
- [715] Replaced custom drivers for the interrupt controllers in favor of the Standalone Xilinx drivers
- Note: The UCOS_Int API now functions as a wrapper for the Xilinx drivers. Existing ISRs should be updated so their prototypes match the UCOS_INT_FNCT_PTR typedef
- [736] OS BSPs now make use of the Xilinx timer APIs
- [737] Updated ISRs in the uC drivers so that they match the new prototype
- [715] [733] Removed obsolete uC drivers
- ucos_scugic, ucos_axiintc, ucos_axitimer, ucos_l2cachec, ucos_scuc, ucos_scutimer, ucos_ttcps
Bug Fixes
· General
· [818] Fixed errors when generating C++ projects
· Zynq Ultrascale+
· [794] Fixed MPU configuration issue in RPU TCP/IP startup