When setting OS_CFG_ISR_POST_DEFERRED_EN
to 0 DEF_DISABLED
, µC/OS-III will disable interrupts before entering a critical section and re-enable them when leaving the critical section.
...
When setting OS_CFG_ISR_POST_DEFERRED_EN
to 0 DEF_DISABLED
, µC/OS-III will disable interrupts before entering a critical section and re-enable them when leaving the critical section.
...